2 Mbit 256Kb x8 Boot Block Single Supply Flash Memory M29F002BB70N1

2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory

■ SINGLE 5V ± 10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS

■ ACCESS TIME: 45 ns

■ PROGRAMMING TIME – 8 µs by Byte typical

■ 7 MEMORY BLOCKS – 1 Boot Block (Top or Bottom Location) – 2 Parameter and 4 Main Blocks

■ PROGRAM/ERASE CONTROLLER – Embedded Byte Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits

■ ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND – Faster Production/Batch Programming

■ TEMPORARY BLOCK UNPROTECTION MODE

■ LOW POWER CONSUMPTION – Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCLES per BLOCK

■ 20 YEARS DATA RETENTION – Defectivity below 1 ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code M29F002BT: B0h

– Top Device Code M29F002BNT: B0h

– Bottom Device Code M29F002BB: 34h

– Bottom Device Code M29F002BNB: 34h

SUMMARY DESCRIPTION

The M29F002B is a 2 Mbit (256Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The M29F002B is fully backward compatible with the M29F002. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

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